nrf_libuarte_drv.c 30 KB

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  1. /**
  2. * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without modification,
  7. * are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. *
  12. * 2. Redistributions in binary form, except as embedded into a Nordic
  13. * Semiconductor ASA integrated circuit in a product or a software update for
  14. * such product, must reproduce the above copyright notice, this list of
  15. * conditions and the following disclaimer in the documentation and/or other
  16. * materials provided with the distribution.
  17. *
  18. * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * 4. This software, with or without modification, must only be used with a
  23. * Nordic Semiconductor ASA integrated circuit.
  24. *
  25. * 5. Any software provided in binary form under this license must not be reverse
  26. * engineered, decompiled, modified and/or disassembled.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
  29. * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  30. * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
  32. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  34. * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37. * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. */
  40. #include "sdk_config.h"
  41. #include "nrf_libuarte_drv.h"
  42. #include "nrf_uarte.h"
  43. #include "nrf_gpio.h"
  44. #include <nrfx_gpiote.h>
  45. #include <../src/prs/nrfx_prs.h>
  46. #define NRF_LOG_MODULE_NAME libUARTE
  47. #if NRF_LIBUARTE_CONFIG_LOG_ENABLED
  48. #define NRF_LOG_LEVEL NRF_LIBUARTE_CONFIG_LOG_LEVEL
  49. #define NRF_LOG_INFO_COLOR NRF_LIBUARTE_CONFIG_INFO_COLOR
  50. #define NRF_LOG_DEBUG_COLOR NRF_LIBUARTE_CONFIG_DEBUG_COLOR
  51. #else // NRF_LIBUARTE_CONFIG_LOG_ENABLED
  52. #define NRF_LOG_LEVEL 0
  53. #endif // NRF_LIBUARTE_CONFIG_LOG_ENABLED
  54. #include "nrf_log.h"
  55. NRF_LOG_MODULE_REGISTER();
  56. #define MAX_DMA_XFER_LEN ((1UL << UARTE0_EASYDMA_MAXCNT_SIZE) - 1)
  57. #define INTERRUPTS_MASK \
  58. (NRF_UARTE_INT_ENDRX_MASK | NRF_UARTE_INT_RXSTARTED_MASK | NRF_UARTE_INT_ERROR_MASK | \
  59. NRF_UARTE_INT_ENDTX_MASK | NRF_UARTE_INT_TXSTOPPED_MASK)
  60. static const nrf_libuarte_drv_t * m_libuarte_instance[2];
  61. /* if it is defined it means that PRS for uart is not used. */
  62. #ifdef nrfx_uarte_0_irq_handler
  63. #define libuarte_0_irq_handler UARTE0_UART0_IRQHandler
  64. #endif
  65. #if NRFX_CHECK(NRF_LIBUARTE_DRV_UARTE0)
  66. void libuarte_0_irq_handler(void);
  67. #endif
  68. #if NRFX_CHECK(NRF_LIBUARTE_DRV_UARTE1)
  69. void libuarte_1_irq_handler(void);
  70. #endif
  71. #if defined(NRF_LIBUARTE_DRV_HWFC_ENABLED)
  72. #define LIBUARTE_DRV_WITH_HWFC NRF_LIBUARTE_DRV_HWFC_ENABLED
  73. #else
  74. #define LIBUARTE_DRV_WITH_HWFC 1
  75. #endif
  76. #define RTS_PIN_DISABLED 0xff
  77. /** @brief Macro executes given function on every allocated channel in the list between provided
  78. * indexes.
  79. */
  80. #define PPI_CHANNEL_FOR_M_N(p_libuarte, m, n, func) \
  81. for (int i = m; i < n; i++) \
  82. { \
  83. if (p_libuarte->ctrl_blk->ppi_channels[i] < PPI_CH_NUM) \
  84. { func(&p_libuarte->ctrl_blk->ppi_channels[i]); } \
  85. }
  86. /** @brief Macro executes provided function on every allocated PPI channel. */
  87. #define PPI_CHANNEL_FOR_ALL(p_libuarte, func) \
  88. PPI_CHANNEL_FOR_M_N(p_libuarte, 0, NRF_LIBUARTE_DRV_PPI_CH_MAX, func)
  89. /** @brief Macro executes provided function on every allocated group in the list. */
  90. #define PPI_GROUP_FOR_ALL(p_libuarte, func) \
  91. for (int i = 0; i < NRF_LIBUARTE_DRV_PPI_GROUP_MAX; i++) \
  92. { \
  93. if (p_libuarte->ctrl_blk->ppi_groups[i] < PPI_GROUP_NUM) \
  94. { func(&p_libuarte->ctrl_blk->ppi_groups[i]); } \
  95. }
  96. /** @brief Allocate and configure PPI channel. Fork is optional and it's not set if NULL.
  97. * Channel parameter is field by the function.
  98. */
  99. static ret_code_t ppi_channel_configure(nrf_ppi_channel_t * p_ch, uint32_t evt,
  100. uint32_t task, uint32_t fork)
  101. {
  102. nrfx_err_t err;
  103. err = nrfx_ppi_channel_alloc(p_ch);
  104. if (err != NRFX_SUCCESS)
  105. {
  106. return NRF_ERROR_NO_MEM;
  107. }
  108. err = nrfx_ppi_channel_assign(*p_ch, evt, task);
  109. if (err != NRFX_SUCCESS)
  110. {
  111. return NRF_ERROR_INTERNAL;
  112. }
  113. if (fork)
  114. {
  115. err = nrfx_ppi_channel_fork_assign(*p_ch, fork);
  116. if (err != NRFX_SUCCESS)
  117. {
  118. return NRF_ERROR_INTERNAL;
  119. }
  120. }
  121. return NRF_SUCCESS;
  122. }
  123. /** @brief Allocate and configure group with one channel. Fetch addresses of enable/disable tasks.*/
  124. static ret_code_t ppi_group_configure(nrf_ppi_channel_group_t * p_ppi_group, nrf_ppi_channel_t ch,
  125. uint32_t * p_en_task, uint32_t * p_dis_task, bool en)
  126. {
  127. nrfx_err_t err;
  128. err = nrfx_ppi_group_alloc(p_ppi_group);
  129. if (err != NRFX_SUCCESS)
  130. {
  131. return NRF_ERROR_NO_MEM;
  132. }
  133. err = nrfx_ppi_channel_include_in_group(ch, *p_ppi_group);
  134. if (err != NRFX_SUCCESS)
  135. {
  136. return NRF_ERROR_INTERNAL;
  137. }
  138. if (en)
  139. {
  140. err = nrfx_ppi_group_enable(*p_ppi_group);
  141. if (err != NRFX_SUCCESS)
  142. {
  143. return NRF_ERROR_INTERNAL;
  144. }
  145. }
  146. *p_en_task = nrfx_ppi_task_addr_group_enable_get(*p_ppi_group);
  147. *p_dis_task = nrfx_ppi_task_addr_group_disable_get(*p_ppi_group);
  148. return NRF_SUCCESS;
  149. }
  150. /** @brief Disable and free PPI channel. */
  151. static void ppi_ch_free(nrf_ppi_channel_t * p_ch)
  152. {
  153. nrfx_err_t err;
  154. err = nrfx_ppi_channel_disable(*p_ch);
  155. ASSERT(err == NRFX_SUCCESS);
  156. err = nrfx_ppi_channel_free(*p_ch);
  157. ASSERT(err == NRFX_SUCCESS);
  158. *p_ch = (nrf_ppi_channel_t)PPI_CH_NUM;
  159. }
  160. /** @brief Disable and free PPI group. */
  161. static void ppi_group_free(nrf_ppi_channel_group_t * p_group)
  162. {
  163. nrfx_err_t err;
  164. err = nrfx_ppi_group_free(*p_group);
  165. ASSERT(err == NRFX_SUCCESS);
  166. *p_group = (nrf_ppi_channel_group_t)PPI_GROUP_NUM;
  167. }
  168. /** @brief Free all channels. */
  169. static void ppi_free(const nrf_libuarte_drv_t * const p_libuarte)
  170. {
  171. PPI_CHANNEL_FOR_ALL(p_libuarte, ppi_ch_free);
  172. PPI_GROUP_FOR_ALL(p_libuarte, ppi_group_free);
  173. }
  174. /** @brief Enable PPI channel. */
  175. static void ppi_ch_enable(nrf_ppi_channel_t * p_ch)
  176. {
  177. nrfx_err_t err;
  178. err = nrfx_ppi_channel_enable(*p_ch);
  179. ASSERT(err == NRFX_SUCCESS);
  180. }
  181. /** @brief Disable PPI channel. */
  182. static void ppi_ch_disable(nrf_ppi_channel_t * p_ch)
  183. {
  184. nrfx_err_t err;
  185. err = nrfx_ppi_channel_disable(*p_ch);
  186. ASSERT(err == NRFX_SUCCESS);
  187. }
  188. /** @brief Enable PPI channels for RX. */
  189. static void rx_ppi_enable(const nrf_libuarte_drv_t * const p_libuarte)
  190. {
  191. PPI_CHANNEL_FOR_M_N(p_libuarte, 0, NRF_LIBUARTE_DRV_PPI_CH_RX_GROUP_MAX, ppi_ch_enable);
  192. }
  193. /** @brief Disable PPI channels for RX. */
  194. static void rx_ppi_disable(const nrf_libuarte_drv_t * const p_libuarte)
  195. {
  196. PPI_CHANNEL_FOR_M_N(p_libuarte, 0, NRF_LIBUARTE_DRV_PPI_CH_RX_GROUP_MAX, ppi_ch_disable);
  197. }
  198. /** @brief Enable PPI channels for TX. */
  199. static void tx_ppi_enable(const nrf_libuarte_drv_t * const p_libuarte)
  200. {
  201. PPI_CHANNEL_FOR_M_N(p_libuarte, NRF_LIBUARTE_DRV_PPI_CH_RX_GROUP_MAX,
  202. NRF_LIBUARTE_DRV_PPI_CH_MAX, ppi_ch_enable);
  203. }
  204. /** @brief Disable PPI channels for TX. */
  205. static void tx_ppi_disable(const nrf_libuarte_drv_t * const p_libuarte)
  206. {
  207. PPI_CHANNEL_FOR_M_N(p_libuarte, NRF_LIBUARTE_DRV_PPI_CH_RX_GROUP_MAX,
  208. NRF_LIBUARTE_DRV_PPI_CH_MAX, ppi_ch_disable);
  209. }
  210. static ret_code_t ppi_configure(const nrf_libuarte_drv_t * const p_libuarte,
  211. nrf_libuarte_drv_config_t * p_config)
  212. {
  213. ret_code_t ret;
  214. uint32_t gr0_en_task = 0;
  215. uint32_t gr0_dis_task = 0;
  216. uint32_t gr1_en_task = 0;
  217. uint32_t gr1_dis_task = 0;
  218. for (int i = 0; i < NRF_LIBUARTE_DRV_PPI_CH_MAX; i++)
  219. {
  220. /* set to invalid value */
  221. p_libuarte->ctrl_blk->ppi_channels[i] = (nrf_ppi_channel_t)PPI_CH_NUM;
  222. }
  223. for (int i = 0; i < NRF_LIBUARTE_DRV_PPI_GROUP_MAX; i++)
  224. {
  225. /* set to invalid value */
  226. p_libuarte->ctrl_blk->ppi_groups[i] = (nrf_ppi_channel_group_t)PPI_GROUP_NUM;
  227. }
  228. if (MAX_DMA_XFER_LEN < UINT16_MAX)
  229. {
  230. ret = ppi_channel_configure(
  231. &p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_ENDTX_STARTTX],
  232. nrf_uarte_event_address_get(p_libuarte->uarte, NRF_UARTE_EVENT_ENDTX),
  233. nrf_uarte_task_address_get(p_libuarte->uarte, NRF_UARTE_TASK_STARTTX),
  234. 0);
  235. if (ret != NRF_SUCCESS)
  236. {
  237. goto complete_config;
  238. }
  239. }
  240. ret = ppi_channel_configure(
  241. &p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_RXRDY_TIMER_COUNT],
  242. nrf_uarte_event_address_get(p_libuarte->uarte, NRF_UARTE_EVENT_RXDRDY),
  243. nrfx_timer_task_address_get(&p_libuarte->timer, NRF_TIMER_TASK_COUNT),
  244. 0);
  245. if (ret != NRF_SUCCESS)
  246. {
  247. goto complete_config;
  248. }
  249. ret = ppi_channel_configure(
  250. &p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_ENDRX_STARTRX],
  251. nrf_uarte_event_address_get(p_libuarte->uarte, NRF_UARTE_EVENT_ENDRX),
  252. nrf_uarte_task_address_get(p_libuarte->uarte, NRF_UARTE_TASK_STARTRX),
  253. nrfx_timer_capture_task_address_get(&p_libuarte->timer, 0));
  254. if (ret != NRF_SUCCESS)
  255. {
  256. goto complete_config;
  257. }
  258. if (p_config->endrx_evt && p_config->rxdone_tsk)
  259. {
  260. ret = ppi_channel_configure(
  261. &p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_ENDRX_EXT_TSK],
  262. nrf_uarte_event_address_get(p_libuarte->uarte, NRF_UARTE_EVENT_ENDRX),
  263. nrfx_timer_capture_task_address_get(&p_libuarte->timer, 0),
  264. p_config->rxdone_tsk);
  265. if (ret != NRF_SUCCESS)
  266. {
  267. goto complete_config;
  268. }
  269. ret = ppi_group_configure(&p_libuarte->ctrl_blk->ppi_groups[NRF_LIBUARTE_DRV_PPI_GROUP_ENDRX_STARTRX],
  270. p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_ENDRX_STARTRX],
  271. &gr0_en_task, &gr0_dis_task, true);
  272. if (ret != NRF_SUCCESS)
  273. {
  274. goto complete_config;
  275. }
  276. ret = ppi_group_configure(&p_libuarte->ctrl_blk->ppi_groups[NRF_LIBUARTE_DRV_PPI_GROUP_ENDRX_EXT_RXDONE_TSK],
  277. p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_ENDRX_EXT_TSK],
  278. &gr1_en_task, &gr1_dis_task, false);
  279. if (ret != NRF_SUCCESS)
  280. {
  281. goto complete_config;
  282. }
  283. ret = ppi_channel_configure(
  284. &p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_EXT_STOP_STOPRX],
  285. p_config->endrx_evt,
  286. nrf_uarte_task_address_get(p_libuarte->uarte, NRF_UARTE_TASK_STOPRX),
  287. nrfx_timer_capture_task_address_get(&p_libuarte->timer, 1));
  288. if (ret != NRF_SUCCESS)
  289. {
  290. goto complete_config;
  291. }
  292. ret = ppi_channel_configure(
  293. &p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_EXT_STOP_GROUPS_EN],
  294. p_config->endrx_evt,
  295. gr0_dis_task,
  296. gr1_en_task);
  297. if (ret != NRF_SUCCESS)
  298. {
  299. goto complete_config;
  300. }
  301. }
  302. if (p_config->rxstarted_tsk || gr1_dis_task)
  303. {
  304. ret = ppi_channel_configure(
  305. &p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_RXSTARTED_EXT_TSK],
  306. nrf_uarte_event_address_get(p_libuarte->uarte, NRF_UARTE_EVENT_RXSTARTED),
  307. gr1_dis_task ? gr1_dis_task : p_config->rxstarted_tsk,
  308. gr1_dis_task ? p_config->rxstarted_tsk : 0);
  309. if (ret != NRF_SUCCESS)
  310. {
  311. goto complete_config;
  312. }
  313. }
  314. if (p_config->startrx_evt)
  315. {
  316. ret = ppi_channel_configure(
  317. &p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_EXT_TRIGGER_STARTRX_EN_ENDRX_STARTX],
  318. p_config->startrx_evt,
  319. nrf_uarte_task_address_get(p_libuarte->uarte, NRF_UARTE_TASK_STARTRX),
  320. gr0_en_task);
  321. if (ret != NRF_SUCCESS)
  322. {
  323. goto complete_config;
  324. }
  325. }
  326. if (p_config->endrx_evt)
  327. {
  328. }
  329. if (LIBUARTE_DRV_WITH_HWFC && (p_config->rts_pin != NRF_UARTE_PSEL_DISCONNECTED))
  330. {
  331. ret = ppi_channel_configure(&p_libuarte->ctrl_blk->ppi_channels[NRF_LIBUARTE_DRV_PPI_CH_RTS_PIN],
  332. nrfx_timer_compare_event_address_get(&p_libuarte->timer, 2),
  333. nrfx_gpiote_set_task_addr_get(p_config->rts_pin),
  334. 0);
  335. if (ret != NRF_SUCCESS)
  336. {
  337. goto complete_config;
  338. }
  339. }
  340. complete_config:
  341. if (ret == NRF_SUCCESS)
  342. {
  343. return ret;
  344. }
  345. ppi_free(p_libuarte);
  346. return ret;
  347. }
  348. void tmr_evt_handler(nrf_timer_event_t event_type, void * p_context)
  349. {
  350. UNUSED_PARAMETER(event_type);
  351. UNUSED_PARAMETER(p_context);
  352. }
  353. ret_code_t nrf_libuarte_drv_init(const nrf_libuarte_drv_t * const p_libuarte,
  354. nrf_libuarte_drv_config_t * p_config,
  355. nrf_libuarte_drv_evt_handler_t evt_handler,
  356. void * context)
  357. {
  358. ret_code_t ret;
  359. IRQn_Type irqn = nrfx_get_irq_number(p_libuarte->uarte);
  360. if (p_libuarte->ctrl_blk->enabled)
  361. {
  362. return NRF_ERROR_INVALID_STATE;
  363. }
  364. p_libuarte->ctrl_blk->evt_handler = evt_handler;
  365. p_libuarte->ctrl_blk->p_cur_rx = NULL;
  366. p_libuarte->ctrl_blk->p_next_rx = NULL;
  367. p_libuarte->ctrl_blk->p_next_next_rx = NULL;
  368. p_libuarte->ctrl_blk->p_tx = NULL;
  369. p_libuarte->ctrl_blk->context = context;
  370. p_libuarte->ctrl_blk->rts_pin = RTS_PIN_DISABLED;
  371. m_libuarte_instance[p_libuarte->uarte == NRF_UARTE0 ? 0 : 1] = p_libuarte;
  372. //UART init
  373. nrf_gpio_pin_set(p_config->tx_pin);
  374. nrf_gpio_cfg_output(p_config->tx_pin);
  375. nrf_gpio_cfg_input(p_config->rx_pin, p_config->pullup_rx ?
  376. NRF_GPIO_PIN_PULLUP : NRF_GPIO_PIN_NOPULL);
  377. nrf_uarte_baudrate_set(p_libuarte->uarte, p_config->baudrate);
  378. nrf_uarte_configure(p_libuarte->uarte, p_config->parity, p_config->hwfc);
  379. nrf_uarte_txrx_pins_set(p_libuarte->uarte, p_config->tx_pin, p_config->rx_pin);
  380. if (LIBUARTE_DRV_WITH_HWFC && (p_config->hwfc == NRF_UARTE_HWFC_ENABLED))
  381. {
  382. if (p_config->cts_pin != NRF_UARTE_PSEL_DISCONNECTED)
  383. {
  384. nrf_gpio_cfg_input(p_config->cts_pin, NRF_GPIO_PIN_PULLUP);
  385. }
  386. if (p_config->rts_pin != NRF_UARTE_PSEL_DISCONNECTED)
  387. {
  388. nrfx_gpiote_out_config_t out_config = NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE(true);
  389. nrfx_err_t err = nrfx_gpiote_init();
  390. if ((err != NRFX_SUCCESS) && (err != NRFX_ERROR_INVALID_STATE))
  391. {
  392. return err;
  393. }
  394. err = nrfx_gpiote_out_init(p_config->rts_pin, &out_config);
  395. if (err != NRFX_SUCCESS)
  396. {
  397. return NRF_ERROR_INTERNAL;
  398. }
  399. nrfx_gpiote_out_task_enable(p_config->rts_pin);
  400. nrf_gpio_cfg_output(p_config->rts_pin);
  401. p_libuarte->ctrl_blk->rts_pin = p_config->rts_pin;
  402. }
  403. nrf_uarte_hwfc_pins_set(p_libuarte->uarte, NRF_UARTE_PSEL_DISCONNECTED, p_config->cts_pin);
  404. }
  405. else if ((p_config->hwfc == NRF_UARTE_HWFC_ENABLED) && !LIBUARTE_DRV_WITH_HWFC)
  406. {
  407. return NRFX_ERROR_INVALID_PARAM;
  408. }
  409. #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRF_LIBUARTE_DRV_UARTE0)
  410. if (irqn == UARTE0_UART0_IRQn)
  411. {
  412. if (nrfx_prs_acquire(p_libuarte->uarte, libuarte_0_irq_handler) != NRFX_SUCCESS)
  413. {
  414. return NRF_ERROR_BUSY;
  415. }
  416. }
  417. #endif // NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRF_LIBUARTE_DRV_UARTE0)
  418. nrf_uarte_int_enable(p_libuarte->uarte, INTERRUPTS_MASK);
  419. NVIC_SetPriority(irqn, p_config->irq_priority);
  420. NVIC_ClearPendingIRQ(irqn);
  421. NVIC_EnableIRQ(irqn);
  422. nrf_uarte_enable(p_libuarte->uarte);
  423. nrfx_timer_config_t tmr_config = NRFX_TIMER_DEFAULT_CONFIG;
  424. tmr_config.mode = NRF_TIMER_MODE_COUNTER;
  425. tmr_config.bit_width = NRF_TIMER_BIT_WIDTH_32;
  426. ret = nrfx_timer_init(&p_libuarte->timer, &tmr_config, tmr_evt_handler);
  427. if (ret != NRFX_SUCCESS)
  428. {
  429. return NRF_ERROR_INTERNAL;
  430. }
  431. ret = ppi_configure(p_libuarte, p_config);
  432. if (ret != NRF_SUCCESS)
  433. {
  434. return NRF_ERROR_INTERNAL;
  435. }
  436. p_libuarte->ctrl_blk->enabled = true;
  437. return NRF_SUCCESS;
  438. }
  439. void nrf_libuarte_drv_uninit(const nrf_libuarte_drv_t * const p_libuarte)
  440. {
  441. IRQn_Type irqn = nrfx_get_irq_number(p_libuarte->uarte);
  442. if (p_libuarte->ctrl_blk->enabled == false)
  443. {
  444. return;
  445. }
  446. p_libuarte->ctrl_blk->enabled = false;
  447. NVIC_DisableIRQ(irqn);
  448. rx_ppi_disable(p_libuarte);
  449. tx_ppi_disable(p_libuarte);
  450. nrf_uarte_int_disable(p_libuarte->uarte, 0xFFFFFFFF);
  451. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTOPPED);
  452. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_RXTO);
  453. nrf_uarte_task_trigger(p_libuarte->uarte, NRF_UARTE_TASK_STOPTX);
  454. nrf_uarte_task_trigger(p_libuarte->uarte, NRF_UARTE_TASK_STOPRX);
  455. while ( (p_libuarte->ctrl_blk->p_tx && !nrf_uarte_event_check(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTOPPED)) ||
  456. (p_libuarte->ctrl_blk->p_cur_rx && !nrf_uarte_event_check(p_libuarte->uarte, NRF_UARTE_EVENT_RXTO)))
  457. {}
  458. p_libuarte->ctrl_blk->p_tx = NULL;
  459. p_libuarte->ctrl_blk->p_cur_rx = NULL;
  460. nrf_uarte_disable(p_libuarte->uarte);
  461. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTARTED);
  462. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTOPPED);
  463. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_ENDTX);
  464. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_ENDRX);
  465. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_RXSTARTED);
  466. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_RXTO);
  467. #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRF_LIBUARTE_DRV_UARTE0)
  468. if (irqn == UARTE0_UART0_IRQn)
  469. {
  470. nrfx_prs_release(p_libuarte->uarte);
  471. }
  472. #endif // NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRF_LIBUARTE_DRV_UARTE0)
  473. nrfx_timer_disable(&p_libuarte->timer);
  474. nrfx_timer_uninit(&p_libuarte->timer);
  475. if (LIBUARTE_DRV_WITH_HWFC && (p_libuarte->ctrl_blk->rts_pin != RTS_PIN_DISABLED))
  476. {
  477. nrfx_gpiote_out_uninit(p_libuarte->ctrl_blk->rts_pin);
  478. }
  479. ppi_free(p_libuarte);
  480. }
  481. ret_code_t nrf_libuarte_drv_tx(const nrf_libuarte_drv_t * const p_libuarte,
  482. uint8_t * p_data, size_t len)
  483. {
  484. if (p_libuarte->ctrl_blk->p_tx)
  485. {
  486. return NRF_ERROR_BUSY;
  487. }
  488. p_libuarte->ctrl_blk->p_tx = p_data;
  489. p_libuarte->ctrl_blk->tx_len = len;
  490. p_libuarte->ctrl_blk->tx_cur_idx = 0;
  491. uint16_t first_chunk;
  492. if ((MAX_DMA_XFER_LEN <= UINT16_MAX) && (len <= MAX_DMA_XFER_LEN))
  493. {
  494. first_chunk = len;
  495. p_libuarte->ctrl_blk->tx_chunk8 = 0;
  496. }
  497. else
  498. {
  499. uint32_t num_of_chunks = CEIL_DIV(len, MAX_DMA_XFER_LEN);
  500. p_libuarte->ctrl_blk->tx_chunk8 = len/num_of_chunks;
  501. first_chunk = p_libuarte->ctrl_blk->tx_chunk8 + len%p_libuarte->ctrl_blk->tx_chunk8;
  502. }
  503. NRF_LOG_WARNING("Started TX total length:%d, first chunk:%d", len, first_chunk);
  504. nrf_uarte_tx_buffer_set(p_libuarte->uarte, p_data, first_chunk);
  505. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTARTED);
  506. nrf_uarte_task_trigger(p_libuarte->uarte, NRF_UARTE_TASK_STARTTX);
  507. if ((MAX_DMA_XFER_LEN <= UINT16_MAX) && (len > MAX_DMA_XFER_LEN))
  508. {
  509. while(nrf_uarte_event_check(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTARTED) == 0)
  510. {
  511. }
  512. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTARTED);
  513. tx_ppi_enable(p_libuarte);
  514. nrf_uarte_tx_buffer_set(p_libuarte->uarte, &p_libuarte->ctrl_blk->p_tx[first_chunk], p_libuarte->ctrl_blk->tx_chunk8);
  515. }
  516. return NRF_SUCCESS;
  517. }
  518. ret_code_t nrf_libuarte_drv_rx_start(const nrf_libuarte_drv_t * const p_libuarte,
  519. uint8_t * p_data, size_t len, bool ext_trigger_en)
  520. {
  521. ASSERT(len <= MAX_DMA_XFER_LEN);
  522. if (p_libuarte->ctrl_blk->p_cur_rx)
  523. {
  524. return NRF_ERROR_BUSY;
  525. }
  526. p_libuarte->ctrl_blk->chunk_size = len;
  527. if (p_data)
  528. {
  529. p_libuarte->ctrl_blk->p_cur_rx = p_data;
  530. nrf_uarte_rx_buffer_set(p_libuarte->uarte, p_data, len);
  531. }
  532. /* Reset byte counting */
  533. nrfx_timer_enable(&p_libuarte->timer);
  534. nrfx_timer_clear(&p_libuarte->timer);
  535. p_libuarte->ctrl_blk->last_rx_byte_cnt = 0;
  536. p_libuarte->ctrl_blk->last_pin_rx_byte_cnt = 0;
  537. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_ENDRX);
  538. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_RXSTARTED);
  539. rx_ppi_enable(p_libuarte);
  540. if (LIBUARTE_DRV_WITH_HWFC && (p_libuarte->ctrl_blk->rts_pin != RTS_PIN_DISABLED))
  541. {
  542. uint32_t rx_limit = len - NRF_LIBUARTE_DRV_HWFC_BYTE_LIMIT;
  543. *(uint32_t *)nrfx_gpiote_clr_task_addr_get(p_libuarte->ctrl_blk->rts_pin) = 1;
  544. nrfx_timer_compare(&p_libuarte->timer, NRF_TIMER_CC_CHANNEL2, rx_limit, false);
  545. }
  546. if (!ext_trigger_en)
  547. {
  548. nrf_uarte_task_trigger(p_libuarte->uarte, NRF_UARTE_TASK_STARTRX);
  549. }
  550. NRF_LOG_DEBUG("Start continues RX. Provided buffer:0x%08X", p_data);
  551. return NRF_SUCCESS;
  552. }
  553. void nrf_libuarte_drv_rx_buf_rsp(const nrf_libuarte_drv_t * const p_libuarte,
  554. uint8_t * p_data, size_t len)
  555. {
  556. if (p_libuarte->ctrl_blk->p_next_rx == NULL)
  557. {
  558. p_libuarte->ctrl_blk->p_next_rx = p_data;
  559. NRF_LOG_DEBUG("RX buf response (next). Provided buffer:0x%08X", p_data);
  560. nrf_uarte_rx_buffer_set(p_libuarte->uarte, p_data, len);
  561. }
  562. else
  563. {
  564. NRF_LOG_DEBUG("RX buf response (mp_next_rx not NULL:0x%08X), Provided buffer:0x%08X",
  565. p_libuarte->ctrl_blk->p_next_rx, p_data);
  566. p_libuarte->ctrl_blk->p_next_next_rx = p_data;
  567. }
  568. if (LIBUARTE_DRV_WITH_HWFC && (p_libuarte->ctrl_blk->rts_pin != RTS_PIN_DISABLED))
  569. {
  570. uint32_t rx_limit = nrfx_timer_capture_get(&p_libuarte->timer, NRF_TIMER_CC_CHANNEL0) +
  571. 2*len - NRF_LIBUARTE_DRV_HWFC_BYTE_LIMIT;
  572. nrfx_timer_compare(&p_libuarte->timer, NRF_TIMER_CC_CHANNEL2, rx_limit, false);
  573. if (p_libuarte->ctrl_blk->rts_manual == false)
  574. {
  575. *(uint32_t *)nrfx_gpiote_clr_task_addr_get(p_libuarte->ctrl_blk->rts_pin) = 1;
  576. }
  577. }
  578. }
  579. void nrf_libuarte_drv_rx_stop(const nrf_libuarte_drv_t * const p_libuarte)
  580. {
  581. rx_ppi_disable(p_libuarte);
  582. NRF_LOG_DEBUG("RX stopped.");
  583. if (LIBUARTE_DRV_WITH_HWFC && (p_libuarte->ctrl_blk->rts_pin != RTS_PIN_DISABLED))
  584. {
  585. *(uint32_t *)nrfx_gpiote_set_task_addr_get(p_libuarte->ctrl_blk->rts_pin) = 1;
  586. }
  587. p_libuarte->ctrl_blk->p_cur_rx = NULL;
  588. nrf_uarte_task_trigger(p_libuarte->uarte, NRF_UARTE_TASK_STOPRX);
  589. }
  590. void nrf_libuarte_drv_rts_clear(const nrf_libuarte_drv_t * const p_libuarte)
  591. {
  592. if (LIBUARTE_DRV_WITH_HWFC && (p_libuarte->ctrl_blk->rts_pin != RTS_PIN_DISABLED))
  593. {
  594. *(uint32_t *)nrfx_gpiote_clr_task_addr_get(p_libuarte->ctrl_blk->rts_pin) = 1;
  595. p_libuarte->ctrl_blk->rts_manual = false;
  596. }
  597. }
  598. void nrf_libuarte_drv_rts_set(const nrf_libuarte_drv_t * const p_libuarte)
  599. {
  600. if (LIBUARTE_DRV_WITH_HWFC && (p_libuarte->ctrl_blk->rts_pin != RTS_PIN_DISABLED))
  601. {
  602. p_libuarte->ctrl_blk->rts_manual = true;
  603. *(uint32_t *)nrfx_gpiote_set_task_addr_get(p_libuarte->ctrl_blk->rts_pin) = 1;
  604. }
  605. }
  606. static void irq_handler(const nrf_libuarte_drv_t * const p_libuarte)
  607. {
  608. if (nrf_uarte_event_check(p_libuarte->uarte, NRF_UARTE_EVENT_ERROR))
  609. {
  610. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_ERROR);
  611. nrf_libuarte_drv_evt_t evt = {
  612. .type = NRF_LIBUARTE_DRV_EVT_ERROR,
  613. .data = { .errorsrc = nrf_uarte_errorsrc_get_and_clear(p_libuarte->uarte) }
  614. };
  615. p_libuarte->ctrl_blk->evt_handler(p_libuarte->ctrl_blk->context, &evt);
  616. }
  617. if (nrf_uarte_event_check(p_libuarte->uarte, NRF_UARTE_EVENT_RXSTARTED))
  618. {
  619. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_RXSTARTED);
  620. nrf_libuarte_drv_evt_t evt = {
  621. .type = NRF_LIBUARTE_DRV_EVT_RX_BUF_REQ,
  622. };
  623. p_libuarte->ctrl_blk->evt_handler(p_libuarte->ctrl_blk->context, &evt);
  624. }
  625. if (nrf_uarte_event_check(p_libuarte->uarte, NRF_UARTE_EVENT_ENDRX))
  626. {
  627. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_ENDRX);
  628. uint32_t endrx_byte_cnt = nrfx_timer_capture_get(&p_libuarte->timer, NRF_TIMER_CC_CHANNEL0);
  629. uint32_t stop_byte_cnt = nrfx_timer_capture_get(&p_libuarte->timer, NRF_TIMER_CC_CHANNEL1);
  630. uint32_t dma_amount = endrx_byte_cnt - p_libuarte->ctrl_blk->last_rx_byte_cnt;
  631. uint32_t pin_amount = stop_byte_cnt - p_libuarte->ctrl_blk->last_pin_rx_byte_cnt;
  632. NRF_LOG_DEBUG("(evt) RX dma_cnt:%d, endrx_cnt:%d, stop_cnt:%d",
  633. dma_amount,
  634. endrx_byte_cnt,
  635. stop_byte_cnt);
  636. p_libuarte->ctrl_blk->last_rx_byte_cnt = endrx_byte_cnt;
  637. p_libuarte->ctrl_blk->last_pin_rx_byte_cnt = stop_byte_cnt;
  638. if (dma_amount || pin_amount)
  639. {
  640. uint32_t chunk0 = (dma_amount > p_libuarte->ctrl_blk->chunk_size) ?
  641. p_libuarte->ctrl_blk->chunk_size : dma_amount;
  642. uint32_t chunk1 = dma_amount - chunk0;
  643. NRF_LOG_DEBUG("RX END chunk0:%d, chunk1:%d, data[0]=%d %d",
  644. chunk0,
  645. chunk1,
  646. p_libuarte->ctrl_blk->p_cur_rx[0],
  647. p_libuarte->ctrl_blk->p_cur_rx[1]);
  648. nrf_libuarte_drv_evt_t evt = {
  649. .type = NRF_LIBUARTE_DRV_EVT_RX_DATA,
  650. .data = {
  651. .rxtx = {
  652. .p_data = p_libuarte->ctrl_blk->p_cur_rx,
  653. .length = chunk0
  654. }
  655. }
  656. };
  657. p_libuarte->ctrl_blk->p_cur_rx = p_libuarte->ctrl_blk->p_next_rx;
  658. p_libuarte->ctrl_blk->p_next_rx = NULL;
  659. if (p_libuarte->ctrl_blk->p_next_next_rx)
  660. {
  661. p_libuarte->ctrl_blk->p_next_rx = p_libuarte->ctrl_blk->p_next_next_rx;
  662. p_libuarte->ctrl_blk->p_next_next_rx = NULL;
  663. nrf_uarte_rx_buffer_set(p_libuarte->uarte,
  664. p_libuarte->ctrl_blk->p_next_rx,
  665. p_libuarte->ctrl_blk->chunk_size);
  666. }
  667. p_libuarte->ctrl_blk->evt_handler(p_libuarte->ctrl_blk->context, &evt);
  668. if ( chunk1 ||
  669. ((dma_amount == p_libuarte->ctrl_blk->chunk_size) && (endrx_byte_cnt == stop_byte_cnt)))
  670. {
  671. NRF_LOG_WARNING("RX END Chunk1:%d", chunk1);
  672. nrf_libuarte_drv_evt_t err_evt = {
  673. .type = NRF_LIBUARTE_DRV_EVT_OVERRUN_ERROR,
  674. .data = {
  675. .overrun_err = {
  676. .overrun_length = chunk1
  677. }
  678. }
  679. };
  680. p_libuarte->ctrl_blk->evt_handler(p_libuarte->ctrl_blk->context, &err_evt);
  681. p_libuarte->ctrl_blk->p_cur_rx = p_libuarte->ctrl_blk->p_next_rx;
  682. p_libuarte->ctrl_blk->p_next_rx = NULL;
  683. }
  684. }
  685. }
  686. if (nrf_uarte_event_check(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTOPPED))
  687. {
  688. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTOPPED);
  689. nrf_libuarte_drv_evt_t evt = {
  690. .type = NRF_LIBUARTE_DRV_EVT_TX_DONE,
  691. .data = {
  692. .rxtx = {
  693. .p_data = p_libuarte->ctrl_blk->p_tx,
  694. .length = p_libuarte->ctrl_blk->tx_len
  695. }
  696. }
  697. };
  698. p_libuarte->ctrl_blk->p_tx = NULL;
  699. p_libuarte->ctrl_blk->evt_handler(p_libuarte->ctrl_blk->context, &evt);
  700. }
  701. if (nrf_uarte_event_check(p_libuarte->uarte, NRF_UARTE_EVENT_ENDTX))
  702. {
  703. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_ENDTX);
  704. size_t amount = nrf_uarte_tx_amount_get(p_libuarte->uarte);
  705. NRF_LOG_DEBUG("(evt) TX completed (%d)", amount);
  706. p_libuarte->ctrl_blk->tx_cur_idx += amount;
  707. if (p_libuarte->ctrl_blk->tx_cur_idx == p_libuarte->ctrl_blk->tx_len)
  708. {
  709. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTOPPED);
  710. nrf_uarte_task_trigger(p_libuarte->uarte, NRF_UARTE_TASK_STOPTX);
  711. }
  712. else
  713. {
  714. size_t rem_len = (p_libuarte->ctrl_blk->tx_len - p_libuarte->ctrl_blk->tx_cur_idx);
  715. if ( rem_len <= MAX_DMA_XFER_LEN)
  716. {
  717. tx_ppi_disable(p_libuarte);
  718. }
  719. else
  720. {
  721. uint8_t * p_buffer = &p_libuarte->ctrl_blk->p_tx[
  722. p_libuarte->ctrl_blk->tx_cur_idx +
  723. p_libuarte->ctrl_blk->tx_chunk8];
  724. if (nrf_uarte_event_check(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTARTED) == 0)
  725. {
  726. NRF_LOG_ERROR("Tx not started yet!");
  727. ASSERT(false);
  728. }
  729. nrf_uarte_event_clear(p_libuarte->uarte, NRF_UARTE_EVENT_TXSTARTED);
  730. nrf_uarte_tx_buffer_set(p_libuarte->uarte,
  731. p_buffer,
  732. p_libuarte->ctrl_blk->tx_chunk8);
  733. }
  734. }
  735. }
  736. }
  737. #if NRF_LIBUARTE_DRV_UARTE0
  738. void libuarte_0_irq_handler(void)
  739. {
  740. irq_handler(m_libuarte_instance[0]);
  741. }
  742. #endif
  743. #if NRF_LIBUARTE_DRV_UARTE1
  744. void UARTE1_IRQHandler(void)
  745. {
  746. irq_handler(m_libuarte_instance[1]);
  747. }
  748. #endif