hardfault_implementation.c 5.9 KB

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  1. /**
  2. * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without modification,
  7. * are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. *
  12. * 2. Redistributions in binary form, except as embedded into a Nordic
  13. * Semiconductor ASA integrated circuit in a product or a software update for
  14. * such product, must reproduce the above copyright notice, this list of
  15. * conditions and the following disclaimer in the documentation and/or other
  16. * materials provided with the distribution.
  17. *
  18. * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * 4. This software, with or without modification, must only be used with a
  23. * Nordic Semiconductor ASA integrated circuit.
  24. *
  25. * 5. Any software provided in binary form under this license must not be reverse
  26. * engineered, decompiled, modified and/or disassembled.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
  29. * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  30. * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
  32. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  34. * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37. * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. */
  40. #include "sdk_common.h"
  41. #if NRF_MODULE_ENABLED(HARDFAULT_HANDLER)
  42. #include "hardfault.h"
  43. #include "nrf.h"
  44. #include "compiler_abstraction.h"
  45. #include "app_util_platform.h"
  46. #ifdef SOFTDEVICE_PRESENT
  47. #include "nrf_soc.h"
  48. #endif
  49. #define NRF_LOG_MODULE_NAME hardfault
  50. #include "nrf_log.h"
  51. #include "nrf_log_ctrl.h"
  52. NRF_LOG_MODULE_REGISTER();
  53. /*lint -save -e14 */
  54. __WEAK void HardFault_process(HardFault_stack_t * p_stack)
  55. {
  56. // Restart the system by default
  57. NVIC_SystemReset();
  58. }
  59. /*lint -restore */
  60. void HardFault_c_handler(uint32_t * p_stack_address)
  61. {
  62. NRF_LOG_FINAL_FLUSH();
  63. #if (__CORTEX_M == 0x04)
  64. #ifndef CFSR_MMARVALID
  65. #define CFSR_MMARVALID (1 << (0 + 7))
  66. #endif
  67. #ifndef CFSR_BFARVALID
  68. #define CFSR_BFARVALID (1 << (8 + 7))
  69. #endif
  70. HardFault_stack_t * p_stack = (HardFault_stack_t *)p_stack_address;
  71. static const char *cfsr_msgs[] = {
  72. [0] = "The processor has attempted to execute an undefined instruction",
  73. [1] = "The processor attempted a load or store at a location that does not permit the operation",
  74. [2] = NULL,
  75. [3] = "Unstack for an exception return has caused one or more access violations",
  76. [4] = "Stacking for an exception entry has caused one or more access violations",
  77. [5] = "A MemManage fault occurred during floating-point lazy state preservation",
  78. [6] = NULL,
  79. [7] = NULL,
  80. [8] = "Instruction bus error",
  81. [9] = "Data bus error (PC value stacked for the exception return points to the instruction that caused the fault)",
  82. [10] = "Data bus error (return address in the stack frame is not related to the instruction that caused the error)",
  83. [11] = "Unstack for an exception return has caused one or more BusFaults",
  84. [12] = "Stacking for an exception entry has caused one or more BusFaults",
  85. [13] = "A bus fault occurred during floating-point lazy state preservation",
  86. [14] = NULL,
  87. [15] = NULL,
  88. [16] = "The processor has attempted to execute an undefined instruction",
  89. [17] = "The processor has attempted to execute an instruction that makes illegal use of the EPSR",
  90. [18] = "The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value",
  91. [19] = "The processor has attempted to access a coprocessor",
  92. [20] = NULL,
  93. [21] = NULL,
  94. [22] = NULL,
  95. [23] = NULL,
  96. [24] = "The processor has made an unaligned memory access",
  97. [25] = "The processor has executed an SDIV or UDIV instruction with a divisor of 0",
  98. };
  99. uint32_t cfsr = SCB->CFSR;
  100. if (p_stack != NULL)
  101. {
  102. // Print information about error.
  103. NRF_LOG_ERROR("HARD FAULT at 0x%08X", p_stack->pc);
  104. NRF_LOG_ERROR(" R0: 0x%08X R1: 0x%08X R2: 0x%08X R3: 0x%08X",
  105. p_stack->r0, p_stack->r1, p_stack->r2, p_stack->r3);
  106. NRF_LOG_ERROR(" R12: 0x%08X LR: 0x%08X PSR: 0x%08X",
  107. p_stack->r12, p_stack->lr, p_stack->psr);
  108. }
  109. else
  110. {
  111. NRF_LOG_ERROR("Stack violation: stack pointer outside stack area.");
  112. }
  113. if (SCB->HFSR & SCB_HFSR_VECTTBL_Msk)
  114. {
  115. NRF_LOG_ERROR("Cause: BusFault on a vector table read during exception processing.");
  116. }
  117. for (uint32_t i = 0; i < sizeof(cfsr_msgs) / sizeof(cfsr_msgs[0]); i++)
  118. {
  119. if (((cfsr & (1 << i)) != 0) && (cfsr_msgs[i] != NULL))
  120. {
  121. NRF_LOG_ERROR("Cause: %s.", (uint32_t)cfsr_msgs[i]);
  122. }
  123. }
  124. if (cfsr & CFSR_MMARVALID)
  125. {
  126. NRF_LOG_ERROR("MemManage Fault Address: 0x%08X", SCB->MMFAR);
  127. }
  128. if (cfsr & CFSR_BFARVALID)
  129. {
  130. NRF_LOG_ERROR("Bus Fault Address: 0x%08X", SCB->BFAR);
  131. }
  132. #if defined(DEBUG)
  133. NRF_BREAKPOINT_COND;
  134. #endif // defined (DEBUG)
  135. #endif // __CORTEX_M == 0x04
  136. HardFault_process((HardFault_stack_t *)p_stack_address);
  137. }
  138. #endif //NRF_MODULE_ENABLED(HARDFAULT_HANDLER)