arm_startup_nrf51.s 8.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261
  1. ; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
  2. ;
  3. ; SPDX-License-Identifier: Apache-2.0
  4. ;
  5. ; Licensed under the Apache License, Version 2.0 (the License); you may
  6. ; not use this file except in compliance with the License.
  7. ; You may obtain a copy of the License at
  8. ;
  9. ; www.apache.org/licenses/LICENSE-2.0
  10. ;
  11. ; Unless required by applicable law or agreed to in writing, software
  12. ; distributed under the License is distributed on an AS IS BASIS, WITHOUT
  13. ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14. ; See the License for the specific language governing permissions and
  15. ; limitations under the License.
  16. ;
  17. ; NOTICE: This file has been modified by Nordic Semiconductor ASA.
  18. IF :DEF: __STARTUP_CONFIG
  19. #ifdef __STARTUP_CONFIG
  20. #include "startup_config.h"
  21. #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
  22. #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
  23. #endif
  24. #endif
  25. ENDIF
  26. IF :DEF: __STARTUP_CONFIG
  27. Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
  28. ELIF :DEF: __STACK_SIZE
  29. Stack_Size EQU __STACK_SIZE
  30. ELSE
  31. Stack_Size EQU 2048
  32. ENDIF
  33. IF :DEF: __STARTUP_CONFIG
  34. Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
  35. ELSE
  36. Stack_Align EQU 3
  37. ENDIF
  38. AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
  39. Stack_Mem SPACE Stack_Size
  40. __initial_sp
  41. IF :DEF: __STARTUP_CONFIG
  42. Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
  43. ELIF :DEF: __HEAP_SIZE
  44. Heap_Size EQU __HEAP_SIZE
  45. ELSE
  46. Heap_Size EQU 2048
  47. ENDIF
  48. AREA HEAP, NOINIT, READWRITE, ALIGN=3
  49. __heap_base
  50. Heap_Mem SPACE Heap_Size
  51. __heap_limit
  52. PRESERVE8
  53. THUMB
  54. ; Vector Table Mapped to Address 0 at Reset
  55. AREA RESET, DATA, READONLY
  56. EXPORT __Vectors
  57. EXPORT __Vectors_End
  58. EXPORT __Vectors_Size
  59. __Vectors DCD __initial_sp ; Top of Stack
  60. DCD Reset_Handler
  61. DCD NMI_Handler
  62. DCD HardFault_Handler
  63. DCD 0 ; Reserved
  64. DCD 0 ; Reserved
  65. DCD 0 ; Reserved
  66. DCD 0 ; Reserved
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD 0 ; Reserved
  70. DCD SVC_Handler
  71. DCD 0 ; Reserved
  72. DCD 0 ; Reserved
  73. DCD PendSV_Handler
  74. DCD SysTick_Handler
  75. ; External Interrupts
  76. DCD POWER_CLOCK_IRQHandler
  77. DCD RADIO_IRQHandler
  78. DCD UART0_IRQHandler
  79. DCD SPI0_TWI0_IRQHandler
  80. DCD SPI1_TWI1_IRQHandler
  81. DCD 0 ; Reserved
  82. DCD GPIOTE_IRQHandler
  83. DCD ADC_IRQHandler
  84. DCD TIMER0_IRQHandler
  85. DCD TIMER1_IRQHandler
  86. DCD TIMER2_IRQHandler
  87. DCD RTC0_IRQHandler
  88. DCD TEMP_IRQHandler
  89. DCD RNG_IRQHandler
  90. DCD ECB_IRQHandler
  91. DCD CCM_AAR_IRQHandler
  92. DCD WDT_IRQHandler
  93. DCD RTC1_IRQHandler
  94. DCD QDEC_IRQHandler
  95. DCD LPCOMP_IRQHandler
  96. DCD SWI0_IRQHandler
  97. DCD SWI1_IRQHandler
  98. DCD SWI2_IRQHandler
  99. DCD SWI3_IRQHandler
  100. DCD SWI4_IRQHandler
  101. DCD SWI5_IRQHandler
  102. DCD 0 ; Reserved
  103. DCD 0 ; Reserved
  104. DCD 0 ; Reserved
  105. DCD 0 ; Reserved
  106. DCD 0 ; Reserved
  107. DCD 0 ; Reserved
  108. __Vectors_End
  109. __Vectors_Size EQU __Vectors_End - __Vectors
  110. AREA |.text|, CODE, READONLY
  111. ; Reset Handler
  112. NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
  113. NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address
  114. NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
  115. Reset_Handler PROC
  116. EXPORT Reset_Handler [WEAK]
  117. IMPORT SystemInit
  118. IMPORT __main
  119. MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
  120. LDR R0, =NRF_POWER_RAMON_ADDRESS
  121. LDR R2, [R0]
  122. ORRS R2, R2, R1
  123. STR R2, [R0]
  124. LDR R0, =NRF_POWER_RAMONB_ADDRESS
  125. LDR R2, [R0]
  126. ORRS R2, R2, R1
  127. STR R2, [R0]
  128. LDR R0, =SystemInit
  129. BLX R0
  130. LDR R0, =__main
  131. BX R0
  132. ENDP
  133. ; Dummy Exception Handlers (infinite loops which can be modified)
  134. NMI_Handler PROC
  135. EXPORT NMI_Handler [WEAK]
  136. B .
  137. ENDP
  138. HardFault_Handler\
  139. PROC
  140. EXPORT HardFault_Handler [WEAK]
  141. B .
  142. ENDP
  143. SVC_Handler PROC
  144. EXPORT SVC_Handler [WEAK]
  145. B .
  146. ENDP
  147. PendSV_Handler PROC
  148. EXPORT PendSV_Handler [WEAK]
  149. B .
  150. ENDP
  151. SysTick_Handler PROC
  152. EXPORT SysTick_Handler [WEAK]
  153. B .
  154. ENDP
  155. Default_Handler PROC
  156. EXPORT POWER_CLOCK_IRQHandler [WEAK]
  157. EXPORT RADIO_IRQHandler [WEAK]
  158. EXPORT UART0_IRQHandler [WEAK]
  159. EXPORT SPI0_TWI0_IRQHandler [WEAK]
  160. EXPORT SPI1_TWI1_IRQHandler [WEAK]
  161. EXPORT GPIOTE_IRQHandler [WEAK]
  162. EXPORT ADC_IRQHandler [WEAK]
  163. EXPORT TIMER0_IRQHandler [WEAK]
  164. EXPORT TIMER1_IRQHandler [WEAK]
  165. EXPORT TIMER2_IRQHandler [WEAK]
  166. EXPORT RTC0_IRQHandler [WEAK]
  167. EXPORT TEMP_IRQHandler [WEAK]
  168. EXPORT RNG_IRQHandler [WEAK]
  169. EXPORT ECB_IRQHandler [WEAK]
  170. EXPORT CCM_AAR_IRQHandler [WEAK]
  171. EXPORT WDT_IRQHandler [WEAK]
  172. EXPORT RTC1_IRQHandler [WEAK]
  173. EXPORT QDEC_IRQHandler [WEAK]
  174. EXPORT LPCOMP_IRQHandler [WEAK]
  175. EXPORT SWI0_IRQHandler [WEAK]
  176. EXPORT SWI1_IRQHandler [WEAK]
  177. EXPORT SWI2_IRQHandler [WEAK]
  178. EXPORT SWI3_IRQHandler [WEAK]
  179. EXPORT SWI4_IRQHandler [WEAK]
  180. EXPORT SWI5_IRQHandler [WEAK]
  181. POWER_CLOCK_IRQHandler
  182. RADIO_IRQHandler
  183. UART0_IRQHandler
  184. SPI0_TWI0_IRQHandler
  185. SPI1_TWI1_IRQHandler
  186. GPIOTE_IRQHandler
  187. ADC_IRQHandler
  188. TIMER0_IRQHandler
  189. TIMER1_IRQHandler
  190. TIMER2_IRQHandler
  191. RTC0_IRQHandler
  192. TEMP_IRQHandler
  193. RNG_IRQHandler
  194. ECB_IRQHandler
  195. CCM_AAR_IRQHandler
  196. WDT_IRQHandler
  197. RTC1_IRQHandler
  198. QDEC_IRQHandler
  199. LPCOMP_IRQHandler
  200. SWI0_IRQHandler
  201. SWI1_IRQHandler
  202. SWI2_IRQHandler
  203. SWI3_IRQHandler
  204. SWI4_IRQHandler
  205. SWI5_IRQHandler
  206. B .
  207. ENDP
  208. ALIGN
  209. ; User Initial Stack & Heap
  210. IF :DEF:__MICROLIB
  211. EXPORT __initial_sp
  212. EXPORT __heap_base
  213. EXPORT __heap_limit
  214. ELSE
  215. IMPORT __use_two_region_memory
  216. EXPORT __user_initial_stackheap
  217. __user_initial_stackheap PROC
  218. LDR R0, = Heap_Mem
  219. LDR R1, = (Stack_Mem + Stack_Size)
  220. LDR R2, = (Heap_Mem + Heap_Size)
  221. LDR R3, = Stack_Mem
  222. BX LR
  223. ENDP
  224. ALIGN
  225. ENDIF
  226. END