bh1745_internal.h 5.7 KB

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  1. /**
  2. * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without modification,
  7. * are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. *
  12. * 2. Redistributions in binary form, except as embedded into a Nordic
  13. * Semiconductor ASA integrated circuit in a product or a software update for
  14. * such product, must reproduce the above copyright notice, this list of
  15. * conditions and the following disclaimer in the documentation and/or other
  16. * materials provided with the distribution.
  17. *
  18. * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * 4. This software, with or without modification, must only be used with a
  23. * Nordic Semiconductor ASA integrated circuit.
  24. *
  25. * 5. Any software provided in binary form under this license must not be reverse
  26. * engineered, decompiled, modified and/or disassembled.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
  29. * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  30. * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
  32. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  34. * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37. * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. */
  40. #ifndef BH1745_INTERNAL_H
  41. #define BH1745_INTERNAL_H
  42. #include "nrf_twi_sensor.h"
  43. #ifdef __cplusplus
  44. extern "C" {
  45. #endif
  46. /**
  47. * @brief Possible sensor addresses.
  48. */
  49. #define BH1745_BASE_ADDRESS_LOW 0x38U
  50. #define BH1745_BASE_ADDRESS_HIGH 0x39U
  51. #define BH1745_MIN_QUEUE_SIZE 5
  52. /**
  53. * @brief Sensor registers.
  54. */
  55. #define BH1745_REG_SYSTEM_CONTROL 0x40
  56. #define BH1745_REG_MODE_CONTROL1 0x41
  57. #define BH1745_REG_MODE_CONTROL2 0x42
  58. #define BH1745_REG_RED_DATA_LSB 0x50
  59. #define BH1745_REG_DINT_DATA_LSB 0x58
  60. #define BH1745_REG_INTERRUPT 0x60
  61. #define BH1745_REG_PERSISTENCE 0x61
  62. #define BH1745_REG_TH_LSB 0x62
  63. #define BH1745_REG_TL_LSB 0x64
  64. #define BH1745_REG_MANUFACTURER_ID 0x92
  65. #define BH1745_DATA_REG_NUM 8
  66. #define BH1745_MANU_ID 0xE0
  67. #define BH1745_PART_ID 0x0B
  68. /**
  69. * @brief System Control register bitmasks.
  70. */
  71. // Default value for system control register.
  72. #define BH1745_DEF_SYSTEM_CONTROL 0x0B
  73. // Bitmasks for sw reset.
  74. #define BH1745_SW_RESET_POS 7
  75. #define BH1745_SW_RESET_MASK (1 << BH1745_SW_RESET_POS)
  76. // Bitmasks for int reset.
  77. #define BH1745_INT_RESET_POS 6
  78. #define BH1745_INT_RESET_MASK (1 << BH1745_INT_RESET_POS)
  79. // Bitmasks for part id.
  80. #define BH1745_PART_ID_POS 0
  81. #define BH1745_PART_ID_MASK (0x3F << BH1745_PART_ID_POS)
  82. /**
  83. * @brief Mode Control 1 register bitmasks.
  84. */
  85. // Bitmasks for meas time.
  86. #define BH1745_MEAS_TIME_POS 0
  87. #define BH1745_MEAS_TIME_MASK (0x07 << BH1745_MEAS_TIME_POS)
  88. /**
  89. * @brief Mode Control 2 register bitmasks.
  90. */
  91. // Bitmasks for valid.
  92. #define BH1745_VALID_POS 7
  93. #define BH1745_VALID_MASK (1 << BH1745_VALID_POS)
  94. // Bitmasks for rgbc en.
  95. #define BH1745_RGBC_EN_POS 4
  96. #define BH1745_RGBC_EN_MASK (1 << BH1745_RGBC_EN_POS)
  97. // Bitmasks for adc gain.
  98. #define BH1745_ADC_GAIN_POS 0
  99. #define BH1745_ADC_GAIN_MASK (3 << BH1745_ADC_GAIN_POS)
  100. /**
  101. * @brief Interrupt register bitmasks.
  102. */
  103. // Bitmasks for int status.
  104. #define BH1745_INT_STATUS_POS 7
  105. #define BH1745_INT_STATUS_MASK (1 << BH1745_INT_STATUS_POS)
  106. // Bitmasks for int latch.
  107. #define BH1745_INT_LATCH_POS 4
  108. #define BH1745_INT_LATCH_MASK (1 << BH1745_INT_LATCH_POS)
  109. // Bitmasks for int source.
  110. #define BH1745_INT_SOURCE_POS 2
  111. #define BH1745_INT_SOURCE_MASK (3 << BH1745_INT_SOURCE_POS)
  112. // Bitmasks for int enable.
  113. #define BH1745_INT_ENABLE_POS 0
  114. #define BH1745_INT_ENABLE_MASK (1 << BH1745_INT_ENABLE_POS)
  115. /**
  116. * @brief Persistence register bitmasks.
  117. */
  118. // Default value for persistence register.
  119. #define BH1745_DEF_PERSISTENCE 0x01
  120. // Bitmasks for persistence.
  121. #define BH1745_PERSISTENCE_POS 0
  122. #define BH1745_PERSISTENCE_MASK (3 << BH1745_PERSISTENCE_POS)
  123. // Default value for high threshold registers.
  124. #define BH1745_DEF_TH 0xFFFF
  125. /**
  126. * @brief Sensor instance information.
  127. */
  128. typedef struct
  129. {
  130. nrf_twi_sensor_t * const p_sensor_data;
  131. uint8_t const sensor_addr;
  132. } bh1745_instance_t;
  133. #define BH1745_INTERNAL_INSTANCE_DEF(_bh1745_inst_name, _p_twi_sensor, _sensor_address) \
  134. static bh1745_instance_t _bh1745_inst_name = \
  135. { \
  136. .p_sensor_data = _p_twi_sensor, \
  137. .sensor_addr = _sensor_address \
  138. }
  139. #ifdef __cplusplus
  140. }
  141. #endif
  142. #endif // BH1745_INTERNAL_H