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- ; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
- ;
- ; SPDX-License-Identifier: Apache-2.0
- ;
- ; Licensed under the Apache License, Version 2.0 (the License); you may
- ; not use this file except in compliance with the License.
- ; You may obtain a copy of the License at
- ;
- ; www.apache.org/licenses/LICENSE-2.0
- ;
- ; Unless required by applicable law or agreed to in writing, software
- ; distributed under the License is distributed on an AS IS BASIS, WITHOUT
- ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- ; See the License for the specific language governing permissions and
- ; limitations under the License.
- ;
- ; NOTICE: This file has been modified by Nordic Semiconductor ASA.
- IF :DEF: __STARTUP_CONFIG
- #ifdef __STARTUP_CONFIG
- #include "startup_config.h"
- #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
- #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
- #endif
- #endif
- ENDIF
- IF :DEF: __STARTUP_CONFIG
- Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
- ELIF :DEF: __STACK_SIZE
- Stack_Size EQU __STACK_SIZE
- ELSE
- Stack_Size EQU 2048
- ENDIF
-
- IF :DEF: __STARTUP_CONFIG
- Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
- ELSE
- Stack_Align EQU 3
- ENDIF
- AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
- Stack_Mem SPACE Stack_Size
- __initial_sp
- IF :DEF: __STARTUP_CONFIG
- Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
- ELIF :DEF: __HEAP_SIZE
- Heap_Size EQU __HEAP_SIZE
- ELSE
- Heap_Size EQU 2048
- ENDIF
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
- __heap_base
- Heap_Mem SPACE Heap_Size
- __heap_limit
- PRESERVE8
- THUMB
- ; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
- __Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler
- DCD NMI_Handler
- DCD HardFault_Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler
- DCD SysTick_Handler
- ; External Interrupts
- DCD POWER_CLOCK_IRQHandler
- DCD RADIO_IRQHandler
- DCD UART0_IRQHandler
- DCD SPI0_TWI0_IRQHandler
- DCD SPI1_TWI1_IRQHandler
- DCD 0 ; Reserved
- DCD GPIOTE_IRQHandler
- DCD ADC_IRQHandler
- DCD TIMER0_IRQHandler
- DCD TIMER1_IRQHandler
- DCD TIMER2_IRQHandler
- DCD RTC0_IRQHandler
- DCD TEMP_IRQHandler
- DCD RNG_IRQHandler
- DCD ECB_IRQHandler
- DCD CCM_AAR_IRQHandler
- DCD WDT_IRQHandler
- DCD RTC1_IRQHandler
- DCD QDEC_IRQHandler
- DCD LPCOMP_IRQHandler
- DCD SWI0_IRQHandler
- DCD SWI1_IRQHandler
- DCD SWI2_IRQHandler
- DCD SWI3_IRQHandler
- DCD SWI4_IRQHandler
- DCD SWI5_IRQHandler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- __Vectors_End
- __Vectors_Size EQU __Vectors_End - __Vectors
- AREA |.text|, CODE, READONLY
- ; Reset Handler
- NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
- NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address
- NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
- Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
-
- LDR R0, =NRF_POWER_RAMON_ADDRESS
- LDR R2, [R0]
- ORRS R2, R2, R1
- STR R2, [R0]
-
- LDR R0, =NRF_POWER_RAMONB_ADDRESS
- LDR R2, [R0]
- ORRS R2, R2, R1
- STR R2, [R0]
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
- ; Dummy Exception Handlers (infinite loops which can be modified)
- NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
- HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
- SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
- PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
- SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
- Default_Handler PROC
- EXPORT POWER_CLOCK_IRQHandler [WEAK]
- EXPORT RADIO_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT SPI0_TWI0_IRQHandler [WEAK]
- EXPORT SPI1_TWI1_IRQHandler [WEAK]
- EXPORT GPIOTE_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT TIMER0_IRQHandler [WEAK]
- EXPORT TIMER1_IRQHandler [WEAK]
- EXPORT TIMER2_IRQHandler [WEAK]
- EXPORT RTC0_IRQHandler [WEAK]
- EXPORT TEMP_IRQHandler [WEAK]
- EXPORT RNG_IRQHandler [WEAK]
- EXPORT ECB_IRQHandler [WEAK]
- EXPORT CCM_AAR_IRQHandler [WEAK]
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT RTC1_IRQHandler [WEAK]
- EXPORT QDEC_IRQHandler [WEAK]
- EXPORT LPCOMP_IRQHandler [WEAK]
- EXPORT SWI0_IRQHandler [WEAK]
- EXPORT SWI1_IRQHandler [WEAK]
- EXPORT SWI2_IRQHandler [WEAK]
- EXPORT SWI3_IRQHandler [WEAK]
- EXPORT SWI4_IRQHandler [WEAK]
- EXPORT SWI5_IRQHandler [WEAK]
- POWER_CLOCK_IRQHandler
- RADIO_IRQHandler
- UART0_IRQHandler
- SPI0_TWI0_IRQHandler
- SPI1_TWI1_IRQHandler
- GPIOTE_IRQHandler
- ADC_IRQHandler
- TIMER0_IRQHandler
- TIMER1_IRQHandler
- TIMER2_IRQHandler
- RTC0_IRQHandler
- TEMP_IRQHandler
- RNG_IRQHandler
- ECB_IRQHandler
- CCM_AAR_IRQHandler
- WDT_IRQHandler
- RTC1_IRQHandler
- QDEC_IRQHandler
- LPCOMP_IRQHandler
- SWI0_IRQHandler
- SWI1_IRQHandler
- SWI2_IRQHandler
- SWI3_IRQHandler
- SWI4_IRQHandler
- SWI5_IRQHandler
- B .
- ENDP
- ALIGN
- ; User Initial Stack & Heap
- IF :DEF:__MICROLIB
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
- ELSE
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
- __user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, = (Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
- ALIGN
- ENDIF
- END
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