; Copyright (c) 2009-2020 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the License); you may ; not use this file except in compliance with the License. ; You may obtain a copy of the License at ; ; www.apache.org/licenses/LICENSE-2.0 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an AS IS BASIS, WITHOUT ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ; NOTICE: This file has been modified by Nordic Semiconductor ASA. IF :DEF: __STARTUP_CONFIG #ifdef __STARTUP_CONFIG #include "startup_config.h" #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 #endif #endif ENDIF IF :DEF: __STARTUP_CONFIG Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE ELIF :DEF: __STACK_SIZE Stack_Size EQU __STACK_SIZE ELSE Stack_Size EQU 16384 ENDIF IF :DEF: __STARTUP_CONFIG Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT ELSE Stack_Align EQU 3 ENDIF AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align Stack_Mem SPACE Stack_Size __initial_sp IF :DEF: __STARTUP_CONFIG Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE ELIF :DEF: __HEAP_SIZE Heap_Size EQU __HEAP_SIZE ELSE Heap_Size EQU 16384 ENDIF AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler DCD NMI_Handler DCD HardFault_Handler DCD MemoryManagement_Handler DCD BusFault_Handler DCD UsageFault_Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler DCD DebugMon_Handler DCD 0 ; Reserved DCD PendSV_Handler DCD SysTick_Handler ; External Interrupts DCD POWER_CLOCK_IRQHandler DCD RADIO_IRQHandler DCD UARTE0_UART0_IRQHandler DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler DCD NFCT_IRQHandler DCD GPIOTE_IRQHandler DCD SAADC_IRQHandler DCD TIMER0_IRQHandler DCD TIMER1_IRQHandler DCD TIMER2_IRQHandler DCD RTC0_IRQHandler DCD TEMP_IRQHandler DCD RNG_IRQHandler DCD ECB_IRQHandler DCD CCM_AAR_IRQHandler DCD WDT_IRQHandler DCD RTC1_IRQHandler DCD QDEC_IRQHandler DCD COMP_LPCOMP_IRQHandler DCD SWI0_EGU0_IRQHandler DCD SWI1_EGU1_IRQHandler DCD SWI2_EGU2_IRQHandler DCD SWI3_EGU3_IRQHandler DCD SWI4_EGU4_IRQHandler DCD SWI5_EGU5_IRQHandler DCD TIMER3_IRQHandler DCD TIMER4_IRQHandler DCD PWM0_IRQHandler DCD PDM_IRQHandler DCD 0 ; Reserved DCD 0 ; Reserved DCD MWU_IRQHandler DCD PWM1_IRQHandler DCD PWM2_IRQHandler DCD SPIM2_SPIS2_SPI2_IRQHandler DCD RTC2_IRQHandler DCD I2S_IRQHandler DCD FPU_IRQHandler DCD USBD_IRQHandler DCD UARTE1_IRQHandler DCD QSPI_IRQHandler DCD CRYPTOCELL_IRQHandler DCD 0 ; Reserved DCD 0 ; Reserved DCD PWM3_IRQHandler DCD 0 ; Reserved DCD SPIM3_IRQHandler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemoryManagement_Handler\ PROC EXPORT MemoryManagement_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT POWER_CLOCK_IRQHandler [WEAK] EXPORT RADIO_IRQHandler [WEAK] EXPORT UARTE0_UART0_IRQHandler [WEAK] EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK] EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK] EXPORT NFCT_IRQHandler [WEAK] EXPORT GPIOTE_IRQHandler [WEAK] EXPORT SAADC_IRQHandler [WEAK] EXPORT TIMER0_IRQHandler [WEAK] EXPORT TIMER1_IRQHandler [WEAK] EXPORT TIMER2_IRQHandler [WEAK] EXPORT RTC0_IRQHandler [WEAK] EXPORT TEMP_IRQHandler [WEAK] EXPORT RNG_IRQHandler [WEAK] EXPORT ECB_IRQHandler [WEAK] EXPORT CCM_AAR_IRQHandler [WEAK] EXPORT WDT_IRQHandler [WEAK] EXPORT RTC1_IRQHandler [WEAK] EXPORT QDEC_IRQHandler [WEAK] EXPORT COMP_LPCOMP_IRQHandler [WEAK] EXPORT SWI0_EGU0_IRQHandler [WEAK] EXPORT SWI1_EGU1_IRQHandler [WEAK] EXPORT SWI2_EGU2_IRQHandler [WEAK] EXPORT SWI3_EGU3_IRQHandler [WEAK] EXPORT SWI4_EGU4_IRQHandler [WEAK] EXPORT SWI5_EGU5_IRQHandler [WEAK] EXPORT TIMER3_IRQHandler [WEAK] EXPORT TIMER4_IRQHandler [WEAK] EXPORT PWM0_IRQHandler [WEAK] EXPORT PDM_IRQHandler [WEAK] EXPORT MWU_IRQHandler [WEAK] EXPORT PWM1_IRQHandler [WEAK] EXPORT PWM2_IRQHandler [WEAK] EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK] EXPORT RTC2_IRQHandler [WEAK] EXPORT I2S_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] EXPORT USBD_IRQHandler [WEAK] EXPORT UARTE1_IRQHandler [WEAK] EXPORT QSPI_IRQHandler [WEAK] EXPORT CRYPTOCELL_IRQHandler [WEAK] EXPORT PWM3_IRQHandler [WEAK] EXPORT SPIM3_IRQHandler [WEAK] POWER_CLOCK_IRQHandler RADIO_IRQHandler UARTE0_UART0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler NFCT_IRQHandler GPIOTE_IRQHandler SAADC_IRQHandler TIMER0_IRQHandler TIMER1_IRQHandler TIMER2_IRQHandler RTC0_IRQHandler TEMP_IRQHandler RNG_IRQHandler ECB_IRQHandler CCM_AAR_IRQHandler WDT_IRQHandler RTC1_IRQHandler QDEC_IRQHandler COMP_LPCOMP_IRQHandler SWI0_EGU0_IRQHandler SWI1_EGU1_IRQHandler SWI2_EGU2_IRQHandler SWI3_EGU3_IRQHandler SWI4_EGU4_IRQHandler SWI5_EGU5_IRQHandler TIMER3_IRQHandler TIMER4_IRQHandler PWM0_IRQHandler PDM_IRQHandler MWU_IRQHandler PWM1_IRQHandler PWM2_IRQHandler SPIM2_SPIS2_SPI2_IRQHandler RTC2_IRQHandler I2S_IRQHandler FPU_IRQHandler USBD_IRQHandler UARTE1_IRQHandler QSPI_IRQHandler CRYPTOCELL_IRQHandler PWM3_IRQHandler SPIM3_IRQHandler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END